FPGA SV/UVM Verification Engineer
Job Description:
FPGA Verification Engineer JD:
5
Years of FPGA Requirement based Verification Extensive experience with System Verilog & UVM Methodology (SV / UVM) Test Bench architecture, Test Bench Troubleshooting, Test Case writing & Execution Video/Image Processing Project Experience Adherence to avionics products, process & documentation DO-254 Process knowledge is desired Remote / Open for Occasional Travel.
US Citizen / Green Card OnlyIND123 Recommended Skills Architecture Fpga Image Processing Problem Solving System Verilog Testbed Estimated Salary: $20 to $28 per hour based on qualifications.
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